1. Technical Field
The invention relates to a bipolar semiconductor device comprising one or more vertical bipolar transistors which have an emitter region, a base region and a collector region, wherein the emitter in standard T-shaped design laterally overlaps the base connection region laterally adjoining the base. The invention also relates to a method for producing such a bipolar semiconductor device.
2. Discussion of Related Art
The performance of silicon-based bipolar transistors (or bipolar junction transistors (BJT)) has been significantly improved in the field of high-speed semiconductors by novel component designs and material components, and by reductions in the size of structures.
Key features of modern vertical high-speed bipolar transistors are described in K. Washio, “SiGe HBT and BiCMOS Technologies”, IEDM, pp. 113-116, 2003. More advanced embodiments can be found in DE 10 2004 061327 and in US 2005/006724.
Known designs contain highly conductive base and collector connection regions which conduct the charge-carrying current from the inner region of the transistor to the respective contact regions. High conductivity is achieved with locally well-controlled doping and, in at least one design, with a monocrystalline base connection region. In order to simultaneously ensure a low capacitance between the base connection region and the other electrical connections of the transistor, the semiconductor regions are separated from each other by insulator regions with low dielectric constants, e.g., by silicon dioxide. The resultant overlaps of the emitter and collector regions with the base are kept as small as possible, which is specifically achieved with self-aligning methods.
“Double polysilicon technology” and “single polysilicon technology” with differential base epitaxy have been established as production methods for silicon-based bipolar (junction) transistors (BJT). The latter method has been developed with technologies for reducing the base resistance and the base-collector capacitance, as described in DE 10 2004 061 327, and with technologies for maximizing the use of self-aligning production methods, as described in US 2005/006724. These methods shall now be discussed in more detail.
a) Double Polysilicon Technology
The interrelationships are illustrated first of all for double-polysilicon technology with reference to FIG. 1, which shows a prior art bipolar transistor in cross-section, the main features of which are the same as the transistor in FIG. 1(a) in the aforementioned publication by Washio. A collector region 20 is bounded at the bottom by a substrate 10 and laterally by wells 11 in the silicon that are filled with silicon dioxide (SiO2) and which are also called “field isolation regions”. Various prior art embodiments use either shallow field isolation regions in the form of shallow trenches (shallow trench isolation, STI), as shown in FIG. 1, or, alternatively, deep trenches.
In the vertical direction, the collector region 20 is composed of a highly doped collector region 21 on the substrate side and a lightly doped collector region 23 above the highly doped region. In the lateral direction, the collector region is adjoined under the STI regions 11 by portions 22 of a collector connection region.
A collector window 34 is formed above the collector region 20, in a layer stack comprising a first insulator layer 30, a polysilicon layer 31 and a second insulator layer 32. By selectively etching the first insulator layer 30, a portion of the polysilicon layer 31 projecting laterally beyond the first insulator region 30 is produced at the lateral edge of the window 34. The end faces of the overhanging portion of polysilicon layer 31 are provided with spacers 50 made of insulator material.
During a selective epitaxy step for producing a base layer 40, silicon fronts grow simultaneously from the exposed portions of the polysilicon layer 31 and the collector region 20 toward each other in a vertical direction and close the gap between the polysilicon layer 31 serving as part of the base connection region and the inner transistor region.
A T-shaped emitter region 60 adjoins the base layer 40 at the bottom with a vertical portion corresponding to the vertical bar of its T-shape, and laterally adjoins the spacers 50. Deposited over the SiGe layer is a cap layer which can receive dopants diffusing out of the emitter during the production process and which can receive at least part of the base-emitter space charge zone. The boundary of the cap layer on the emitter side is indicated by a broken separating line in the emitter. Portions of the emitter 60, corresponding to the horizontal bar of the T-shape, rest sideways on the second insulator layer 32.
Another typical feature of this known transistor design is a selectively implanted collector (SIC) region in which the level of collector doping is raised locally in order to simultaneously minimize the collector-base transit time, the base-collector capacitance and the collector resistance in a way that permits good high-speed properties on the part of the transistor.
In this design, various dimensions are self-aligning: firstly, the overlap between the polysilicon layer 31 and the selectively grown base 40, which simultaneously has an importance share of the base-collector capacitance. The lateral distance between the highly doped polysilicon layer 31 and the emitter window 62 is likewise self-aligned by spacers 50. The position of the SIC region 33 is likewise self-aligning in relation to the collector window 34 and to the emitter window 62, in that the opening provided by means of spacers 50 in the polysilicon layer 31 serves as masking.
b) Single Polysilicon Technology
FIG. 2 shows a cross-sectional view of another vertical bipolar transistor according to the prior art. A portion of the inner transistor region is shown schematically, as are the adjoining base connection and collector connection regions. The transistor in FIG. 2 has a single-polysilicon structure with a differentially deposited base. Essential features of the collector design are identical to those of the double-polysilicon variant shown in FIG. 1.
A collector 120 is enclosed from below by a substrate 110 and toward the sides by STI regions 111. The collector 120 has a highly doped portion 121 at the substrate side. Toward the surface, the collector has a lightly doped portion 123. Unlike the double-polysilicon structure shown in FIG. 1, in which the polysilicon layer 31 is deposited independently of the base layer, the single-polysilicon variant involves depositing polycrystalline semiconductor material 130 during the differential epitaxy step for producing the base on the field isolation regions, wherein said polycrystalline semiconductor material 130 can be used as part of the base connection region.
For the reasons mentioned further above, an SIC region 133 is used in the same manner as in the double-polysilicon variant. Known single-polysilicon transistor structures also typically have more weakly doped silicon regions in lateral proximity to the SIC region 133, which cause undesired capacitances between the base connection and collector regions.
As in the double-polysilicon variant, the emitter is executed as a T-shape, the width of the overlap 161 beyond the emitter window 162 being photolithographically aligned, as in double-polysilicon technology.
c) Vertically Insulated Monocrystalline Base Connection Region Technology
FIG. 3 shows a cross-section of a third bipolar transistor according to the prior art. A section of the inner transistor regions is shown schematically, as are the adjacent base connection and collector connection regions. The transistor in FIG. 3 has a single-polysilicon structure with a differentially deposited base, which in contrast to the transistor shown in FIG. 2 permits the formation of a monocrystalline base connection region and has a reduced parasitic base-collector capacitance due to the special structure of the collector region.
A collector 220 is enclosed from below by a substrate 210 and toward the sides by STI regions 211. The collector 220 has a highly doped portion 221 on the substrate side.
The transistor has a first semiconductor electrode which is made of monocrystalline semiconductor material of a second conductivity type and which is disposed in an opening of the insulation region, said electrode being configured either as a collector or as an emitter and having a first vertical portion which is enclosed by the insulation region in a lateral direction perpendicular to the vertical direction, and an adjoining second vertical portion further distanced in the vertical direction from the interior of the substrate, wherein said second portion is not enclosed laterally by the insulation region.
The transistor also has a second semiconductor electrode made of a semiconductor material of the second conductivity type, which is embodied as the other type of semiconductor electrode, i.e., as an emitter or alternatively as a collector, a base made of monocrystalline semiconductor material of the first conductivity type disposed between the collector and the emitter, and a base connection region which has a monocrystalline portion that surrounds the base in the lateral direction and that, seen from the base, laterally surrounds the second vertical portion of the first semiconductor electrode lying further toward the substrate interior, said portion also resting directly on the insulation region with its underside facing the substrate interior, and which is referred to as a vertically insulated monocrystalline base connection region.
Here, the emitter window 262 is positioned self-aligningly with respect to the base connection region and with respect to the SIC, whereas the width of the overlap 261 of the emitter beyond the emitter window 262 and the base connection region 230 is photolithographically aligned.
d) US 2005/006724
FIG. 4 shows a cross-section of a fourth bipolar transistor according to the prior art. A section of the inner transistor region is shown schematically, as are the adjacent base connection and collector connection regions. The transistor shown in FIG. 4 has a structure with a differentially deposited base, said structure being characterized by extensive use of self-aligning methods.
A collector 320 is bounded at the bottom by a substrate 310. In contrast to the preceding embodiments of prior art transistors, the collector 320 is guided over a connection region 321 and under insulation region 311 to the collector contact region 322.
The transistor is formed in a window of a base connection region made of polysilicon 331, said region being opened above the region of the collector 320.
By means of differential epitaxy, a monocrystalline base layer stack 307 and a weakly doped cap layer 308 are deposited over the collector region, while a polycrystalline connection 310 is formed at the side walls of the base connection region.
L-shaped spacers 350, which are likewise formed inside the window in the base connection region 331, separate the emitter 360 from the base connection region 331. In this embodiment, the entire emitter is self-aligning with respect to the opening in the base connection region.
The width of the region of the T-shaped emitter 360 which projects beyond the emitter window 362, said region being separated from a base connection region 309 by the lower part of spacers 350, is aligned with the opening in the base connection region 331 and hence also with the emitter window 362 by the L-shaped spacers 350.